Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
• 12 years of experience in physical design or custom layout.
  
• Experience leading tape-outs for advanced nodes.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience in custom digital circuits for analog blocks.
• Experience with Electromagnetic Modeling (EM) and its impact on physical layout (e.g., inductors, T-lines).
• Expertise in Co-Packaged Optics (CPO) physical implementation and advanced packaging (2.5D/3D).
• Understanding of device physics and its impact on layout parasitics and performance.
• Excellent strategic outlook for the intersection of AI-driven layout and traditional custom design.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As the Technical Lead for Custom Digital Circuit Design, you will define the design standards and framework for our next-generation custom silicon, moving beyond traditional place-and-route to specialize in transistor-level custom digital circuit design.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $240,000-$334,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.


Responsibilities

• Define the global back-end and physical design methodology, driving the transition to automated Analog and Mixed-Signal (AMS) flows and "Layout-Aware" design.
• Evaluate and de-risk new process features in GAA (Gate-All-Around) nodes, including backside power delivery and buried power rails, specifically for high-speed analog use cases.
• Drive the long-term roadmap for area and power density, ensuring Google's physical layers remain the most efficient in the industry.
• Architect test-chip strategies to characterize silicon behavior (e.g., process monitors, ring oscillators) before committing to high-volume production.
• Provide technical leadership and mentorship to executive engineers, fostering a culture of innovation and engineering excellence in custom circuit design.

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Requisition #: 134739682444354246

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