Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience with IP development or SoC integration.
• 4 years of experience managing the design team or SoC project.
• Experience in ASIC development with system verilog.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with ASIC design methodologies for clock domain checks, reset checks, and low power design.
• Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
• Knowledge of high-performance and low-power design techniques.
• Knowledge of ASIC Verification, DFT, synthesis, STA, or physical design.
• Knowledge of FPGA and emulation platforms.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $192,000-$278,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead a team of RTL Design engineers performing tasks related to IP development and/or SOC Design.
  
• Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.).
  
• Participate with architecture and system design teams in architecture definition, die area estimation, power optimization, and performance enhancements.
  
• Work closely with the multi-site cross-functional teams: Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
  
• Define microarchitecture for a subsystem/SoC top-level.
  

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Requisition #: 76644148764910278

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