Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 1 year of experience with physical design.
• Experience with scripting languages such as Perl, Python, or Tcl.
• Experience with Synopsys/Cadence PnR tools and backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).
• Experience in static timing analysis (STA), including experience defining timing corners, margins, and derates.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with constraints, synthesis or clock tree synthesis (CTS).
• Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC design.
• Experience working with external partners on physical design (PD) closure.
• Understanding of DFT including Scan, MBIST and LBIST.
• Understanding of performance, power and area (PPA) trade-offs.

About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full-chip Signoff teams. Additionally, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $116000 - $166000 (USD) 15% bonus target equity benefits

Learn more about benefits at Google.

Responsibilities

• Participate in the Physical Design (PD) of blocks for complex TPU chips.
• Contribute to the design and closure of the subchip and individual blocks from RTL-to-GDS.
• Collaborate with RTL/Design and PD teams to achieve the best PPA possible, including conducting feasibility studies for new microarchitectures as well as optimizing runs for best Quality of Results (QoR).
• Create and maintain policies, processes, procedures, methods, tests, and documentation of silicon deliverables for the purpose of enhancing and promoting high efficiency, productivity, and sustainability.
• Identify test requirements, select appropriate tools, methods, and approach, and carry out testing of Silicon systems, influence designs to enable and enhance testing, validation, and debugging.

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Requisition #: 116110842792944326

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