Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in RTL design in Verilog/System Verilog.
• 5 years of experience in micro-architecture definition.

Preferred qualifications:

• Experience in physical design.
• Knowledge of high-performance and low-power architectures for ML acceleration.
• Knowledge of transformer-based large language models.
• Knowledge of processor core SoC integration.
• Knowledge or understanding of high level synthesis.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Artificial intelligence will be one of humanity's most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority.

We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $256000 - $279000 (USD) 20% bonus target

Learn more about benefits at Google.

Responsibilities

• Work in a fast and interdisciplinary team bringing together experts from Machine Learning, Hardware, Programming Languages, and Systems.
• Participate in high performance machine learning accelerator architecture, micro-architecture, and RTL design.
• Select and integrate in-house and third party IP.
• Explore various trade-offs of future architecture designs in terms of performance, power, energy, and area.

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Requisition #: 138097144379646662

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