Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  
• 10 years of experience in silicon validation and testing.
• 5 years of experience in technical leadership with/without direct reports.

Preferred qualifications:

• 10 years of experience in post-silicon validation and bring-up.
• Experience with advanced DFT techniques such as hierarchical DFT, compression, and diagnosis.
• Experience with FPGA-based emulation.
• Proficiency in hardware description languages (Verilog, SystemVerilog).
• Excellent problem-solving/investigative skills, with communication and teamwork abilities.

About the job
In this role, you will manage post-silicon validation specification and execution. You will also be responsible for post silicon validation specification and execution. You will have an understanding of digital verification, testing, and all aspects of micro display validation.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $240,000-$334,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• 
  Lead the bring-up process on debugging stations, including FPGA-based platforms, upon the arrival of the first silicon. Assist in the analysis of silicon failures and collaborate with design and test engineering teams to ascertain root causes.
  
• Advocate enhancements in the validation flow, encompassing new tools, methodologies, and scripts, to significantly boost efficiency and coverage.
• Partner with the Architecture, Physical Design, and Test Engineering teams to ensure the integration and execution of the Design-for-Test (DFT) plan.
• Work in close conjunction with the verification team to meticulously define test plans, formulate assertions, and debug logic issues, thereby ensuring functional correctness.

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Requisition #: 82514467115410118

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