Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in both Design Verification (UVM/SystemVerilog) and Hardware Emulation.
• Experience reproducing post-silicon lab failures in emulation or simulation environments.
• Experience with industry-standard debug tools (e.g., Synopsys Verdi, Cadence SimVision), with experience using scripting languages (Python, TCL, Bash) to automate debug workflows.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Understanding of CPU/SoC micro-architecture.
• Knowledge of standard high-speed protocols (e.g., PCIe, CXL, AMBA).
• Expertise parsing post-silicon diagnostic artifacts like scan dumps, OS logs, and JTAG traces.
• Excellent communication skills to translate complex technical issues across distinct engineering domains.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $237000 (USD) 15% bonus target equity benefits

Learn more about benefits at Google.

Responsibilities

• Act as the critical bridge between Emulation, Design Verification (DV), and Register-Transfer Level (RTL) teams to accelerate root-cause analysis.
• Correlate DV simulation failures with emulation results by analyzing SystemVerilog/UVM testbenches.
• Lead post-silicon debug by analyzing lab artifacts (scan dumps, software logs) to reproduce silicon bugs in emulation.
• Create tools and scripts to automate debug pipelines and bridge software workloads with hardware triggers.
• Utilize deep micro-architecture knowledge to rapidly isolate complex hardware issues.

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Requisition #: 97437711190631110

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