Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience verifying digital logic at RTL using SystemVerilog.
• Experience verifying digital IP and subsystems.

Preferred qualifications:

• Master's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
• Experience creating and utilizing UVM-based verification environments.
• Experience with image processing, computer vision, or machine learning applications.
• Familiarity with ASIC standard interfaces and memory system architecture.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $198000 (USD) 15% bonus target equity benefits

Learn more about benefits at Google.

Responsibilities

• Plan the verification of complex digital design blocks by analyzing specifications and collaborating with design engineers to identify critical scenarios.
• Develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs using SystemVerilog Assertions (SVA).
• Design and implement comprehensive coverage measures to target functional stimulus and corner-case scenarios.
• Debug test failures in collaboration with design engineers to ensure functionally correct digital blocks.
• Analyze coverage data to identify verification gaps and track progress toward tape-out milestones.

${qualifications}${responsibilities}
Requisition #: 93872020650894022

pca3lyuhf