Description

Minimum qualifications:

• Bachelor's degree in a technical field, or equivalent practical experience.
  
• 5 years of experience in program management.
  
• Experience in sourcing, commodity management, or supply chain operations within the semiconductor industry.
• Experience with foundry/fabless environments and semiconductor process packaging flows.

Preferred qualifications:

• 5 years of experience managing cross-functional or cross-team projects.
• Experience in advanced packaging technology (e.g., Chip on Wafer on Substrate (CoWoS), System on Integrated Chips (SoIC), Embedded Multi-die Interconnect Bridge (EMIB)) and next-generation node qualification.
• Ability to influence cross-functional global teams and manage complex supplier relationships on the ground.
• Ability to communicate in English and Mandarin fluently to support regional supplier management.

About the job
A problem isn't truly solved until it's solved for all. That's why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You'll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.

In this role, you will focus on securing leading-edge foundry nodes and sophisticated 2.5D/3D packaging solutions. You will be responsible for designing a premier supply chain that integrates standard foundry oversight with complex technologies. Acting as a vital link between external partners and internal engineering, you will ensure technology alignment, capacity assurance, and competitive pricing for Google's custom silicon initiatives. You will be instrumental in the design, verification, and implementation of complex digital integrated circuits from concept to production, with a particular emphasis on ensuring seamless integration and outcomes with our external technology providers. You will work on technologies that are critical to our next-generation products, contributing to the full lifecycle of ASIC development while actively managing our external technical engagements.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $163,000-$237,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.


Responsibilities

• Lead the selection and management of foundry partners for advanced process nodes.
• Lead high-stakes negotiations for pricing, business models, and Long-Term Agreements (LTAs) to secure wafer capacity and packaging slots.
• Manage the transition from New Product Introduction (NPI) to High-Volume Manufacturing (HVM), monitoring capacity bring-up and resolving bottlenecks.
• Partner with system architects to establish chip and block-level specifications while defining micro-architectures and design partitioning.
• Develop multi-sourcing and dual-sourcing strategies to mitigate geopolitical and supply chain risks across the global semiconductor landscape.

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Requisition #: 105565723023024838

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