Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12 years of experience in physical design or custom layout.
  
• Experience leading tape-outs for advanced nodes.

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience in Electromagnetic Modeling (EM) and its impact on physical layout (Inductors, T-lines).
• Experience in Co-Packaged Optics (CPO) physical implementation.
• Experience representing the organization in Foundry Advisory Boards or industry standards.
• Understanding the intersection of AI-driven layout and traditional custom design.

About the jobIn this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As the architect for Google's high-speed internal connections, you will set the design standards for custom silicon. You will ensure our physical design methods can support data speeds of 1.6T and above while maintaining high manufacturing reliability and performance. Your goal is to create the design framework for future hardware, solving complex engineering challenges in the latest manufacturing processes.The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're behind Google's groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $240,000-$334,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Define the global Back-end and Physical Design methodology, driving the transition to automated AMS flows and "Layout-Aware" design.
• Evaluate and de-risk new process features in GAA (Gate-All-Around) nodes (e.g., Backside Power Delivery, Buried Power Rails) for high-speed analog use cases.
• Drive the long-term Roadmap for Area and Power density, ensuring our PHYs remain the most efficient in the industry.
• Act as the primary liaison with foundries to optimize Design for Manufacturing (DFM) and maximize yield for massive TPU-scale chips.
• Architect test-chip strategies to characterize silicon behavior (Process Monitors, Ring Oscillators) before high-volume production.

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Requisition #: 88357395385721542

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