Description

Job Details:

Job Description:

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

The Role:

We are seeking a highly skilled and hands-on DFT/STA Engineer to join our full-chip timing organization supporting next-generation AI processors. This is a backend role focused on PrimeTime-based DFT-mode timing constraints, constraints hygiene, and signoff readiness. The role requires deep understanding of Tessent DFT architecture and implementation concepts-including Streaming Scan Network (SSN), IJTAG/test access integration (HTAP, TAPLink), and memory test/repair (MBIST/BISR)-and the ability to translate DFT intent into correct, auditable timing constraints and stable signoff across all DFT modes. You will collaborate closely with DFT architecture/implementation teams, RTL, Physical Design (Synthesis/CTS/PnR), and Product/Test Engineering to enable first-pass silicon success.

Key Responsibilities:
DFT Timing Constraints and PrimeTime Signoff Ownership

• Own the definition, generation, validation, and maintenance of comprehensive DFT timing constraints (SDC) in Synopsys PrimeTime for modes including Scan Shift, Scan Capture (slow/fast as applicable), JTAG/IJTAG, and Memory BIST.
• Own PrimeTime STA signoff for DFT modes at both block and top level across relevant corners and operating conditions; ensure correctness, coverage, and auditable exception governance (false paths, multicycle paths, case analysis).
• Establish and enforce constraints hygiene standards: mode separation, exception audits, constraint reviews/linting, and regression strategies to prevent drift and late-cycle surprises.

Tessent DFT Architecture Collaboration (SSN / IJTAG / HTAP / TAPLink / MBIST)

• Partner with DFT architecture and implementation teams to support Tessent-based integration, including Streaming Scan Network (SSN) architecture/implementation considerations, IJTAG/test access strategy (HTAP, TAPLink), and MBIST/BISR collateral and constraints needs.
• Translate DFT architecture intent into timing assumptions and constraints that are signoff-safe, traceable, and robust across integration drops.
• Debug complex DFT insertion/integration issues (RTL and gate-level netlists) that impact test-mode timing closure and signoff.

Backend Closure Execution (PD/CTS/ECO)

• Drive DFT-mode timing convergence by partnering with Synthesis/CTS/PnR teams to debug complex violations and guide/implement ECO strategies when needed.
• Develop repeatable signoff checklists and reporting that clearly communicate DFT-mode signoff readiness and risks to stakeholders.

Flow Improvement and Automation

• Improve DFT/STA flows through automation (Tcl required; Python/shell preferred): multi-mode runs, report triage, regression checks, and signoff dashboards.
• Identify and implement methodology improvements that increase efficiency, reduce churn, and improve confidence in DFT-mode signoff.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

Bachelors & 8+ years or Masters & 6+ years in Electrical Engineering, Computer Engineering, or related field with 6+ years in the following:

• DFT and/or STA for complex SoCs with demonstrated ownership of PrimeTime-based signoff and constraints.
• Ownership of DFT-mode SDC development and PrimeTime STA signoff (PrimeTime-only signoff environment).
• Tessent DFT architecture concepts and integration flows, including Streaming Scan Network (SSN), IJTAG/test access integration (HTAP, TAPLink), and MBIST/BISR fundamentals.
• CDC/RDC fundamentals and their interaction with constraints, clocks, resets, and test modes.
• Verilog/SystemVerilog; ability to read/debug gate-level netlists and DFT-inserted structures.
• Tcl required; Python and/or shell strongly preferred.

Preferred Qualifications:

• Hands-on Tessent flow experience (architecture-to-implementation), including SSN/IJTAG integration across hierarchical SoC/IP environments.
• Strong track record owning DFT-mode signoff hygiene for Scan Shift / Slow Capture and MBIST/JTAG across large MMMC environments.
• Experience with signoff guardrails and quality checks (lint, CDC/RDC, LEC, Spyglass DFT or equivalents; low-power intent checks when applicable).
• Proven ability to drive cross-team closure with PD and DFT stakeholders under aggressive schedules.

Job Type:
Experienced Hire

Shift:
Shift 1 (United States of America)

Primary Location:
US, California, Folsom

Additional Locations:

Business group:
At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust
N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Requisition #: JR0282918

pca3lyuhf