Description

Job Details:

Job Description:

Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision.

Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet.

Life at Intel: https://jobs.intel.com/en/life-at-intel

Intel is seeking a Senior Design Verification Engineer for the Silicon Chassis team. In this role, you will own end-to-end verification of critical chassis and interconnect IP blocks from planning through signoff. You will drive quality in testbench architecture, test plan and coverage closure while working closely with architecture, design, and software teams. This position requires strong technical depth in DV methodologies, protocol verification, and memory subsystem behavior, with enough breadth in RTL, physical design, and CAD to contribute across traditional discipline boundaries. AI-assisted workflows are part of everyday development here. Consistent execution against schedule and quality goals is expected.

Responsibilities include but are not limited to:

• Own verification planning and execution for key IP features across IP and subsystem integration points
• Build scalable verification environments and targeted testplans with reusable testbenches, checkers, VIPs, and behavioral models
• Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality
• Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
• Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
• Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows
• Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality

Qualifications:

You must possess the minimum qualifications below to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's Degree in Electrical Engineering, Computer Science, or related field, with 9+ years of relevant experience OR Master's degree in Electrical Engineering, Computer Science, or related field, with 6+ years of relevant experience in design verification; extensive background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification
• Proven deep expertise in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models- Demonstrated experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security features
• Strong background in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
• Advanced hands-on coding proficiency across SystemVerilog/UVM, C/C++, Python, and build systems; comfort using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral
• Working familiarity with RTL, physical design, and CAD tool flows; enough to read, review, and contribute outside core DV responsibilities
• Excellent communication and organizational skills with a track record of delivering high-quality silicon on schedule; able to adapt as tools, methodologies, and role definitions evolve

Preferred Qualifications:

• 12+ years of relevant experience in design verification; extensive background in IP DV with significant, demonstrated experience in subsystem and SoC-level verification
• Hands-on experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification; track record of combining formal and simulation for unified bug closure
• Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associated software stacks

We are constantly working on making a more connected and intelligent future, and we need your help. Change tomorrow. Start today.

Interview Tips: https://www.intel.com/content/www/us/en/jobs/hiring.html

Job Type:
Experienced Hire

Shift:
Shift 1 (United States of America)

Primary Location:
US, California, Santa Clara

Additional Locations:

Business group:
The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust
N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .

Annual Salary Range for jobs which could be performed in the US: $190,610.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Requisition #: JR0282231

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