Description

Job Details:

Job Description:

Join Intel's Mission to Transform Tomorrow :

The Silicon and Platform Engineering ( SPE ) team stands at the forefront of Intel's semiconductor innovation, driving the development and optimization of cutting-edge silicon technologies that power the world's most advanced computing solutions. As a critical bridge between design and manufacturing, S PE ensures Intel's processors meet the highest standards of performance, reliability, and quality. Our team of world-class engineers tackles the most complex challenges in silicon validation, leveraging state-of-the-art debug methodologies and pioneering new techniques that define industry standards. Within S PE , the Pathfinding Engineer plays a pivotal role in advancing our post-silicon analysis capabilities, developing breakthrough tools and methodologies that enable rapid debug, failure analys is , and fault isolation (Debug/FA/FI). This position offers the unique opportunity to work at the intersection of hardware engineering and technology innovation, directly contributing to the silicon solutions that will shape the future of computing, artificial intelligence, and digital transformation across industries worldwide.

Position Overview : We're seeking a skilled Pathfinding Engineer to lead post-silicon debug initiatives and advance optical tools development. This role combines hands-on technical expertise with strategic innovation to solve complex semiconductor challenges.

Key Responsibilities

Technical Execution:

• Develop and implement cutting-edge debug methodologies.
• Debug failing units using functional testers and advanced fault isolation techniques ( Ebeam , LIT, XADA, TADA, LVP, IREM, TIVA , FIB , C ircuit E dit , etc . ).
• Apply deep product architecture knowledge to identify failures efficiently and accurately.

Collaboration & Communication:

• Partner closely with FIB, test, and design engineering teams to analyze and resolve complex issues.
• Translate technical findings into clear, actionable insights for stakeholders.
• Ensure customer requirements are understood and delivered on schedule.

I nnovation & Leadership:

• Define current and future debug lab requirements for Intel.
• Lead development projects that advance post-silicon debug capabilities.
• P repare for paradigm shifts in process technology roadmaps to ensure successful product launches.
• Create new test patterns, software solutions, and proof-of-concept demonstrations.
• Provide cross-functional technical leadership and knowledge sharing.

What We're Looking For:

• Exceptional problem-solving abilities and analytical thinking.
• Self-motivated professional who thrives with minimal supervision.
• Strong passion for semiconductor design and deep technical curiosity.
• Excellent communication and collaboration skills.
• Eagerness to learn and adapt to emerging technologies.

Growth Opportunities: While comprehensive training on tools, techniques, and product architecture will be provided, you'll be expected to continuously expand your expertise through collaboration with Intel's global engineering teams. Ready to shape the future of technology? Let's create something extraordinary together.

Qualifications:

Minimum Qualifications

• US Citizenship Required .
• Bachelors of Science degree in electrical/electronic e ngineering, computer engineering/ science or any STEM related field of study .
• 2+ years of hands-on experience in any of the following:
  • Computer architecture (x86) VLSI circuit design or device physics or process engineering.
  • Working knowledge of Computer systems (i.e., Windows, LINUX, and UNIX).
  • Experience with one of the following program languages (Python, Java, or C++).

• 4+ years of hands-on experience in any of the following:
  • Post silicon debug methodology.
  • Technology Pathfinding experience.
  • Experience with product improvements to enhance performance, yield, quality, or reliability.
  • Experience with of next generation Si, Product, and Package technologies.
  • Experience with failure analysis fault isolations or debug tool sets.

Preferred Qualifications

• Post Graduate degree in E lectrical / C o mputer E ngineering or any STEM related degree .
• Experience Influencing the IP/SoC design decisions and/or pre-/ post- validation methods by doing validation gap analysis.
• Strong hands-on lab experience .
• Experience with CAD tools: Cadence Allegro or Mentor Expedition, or equivalent .
• Statistical/data analysis (MATLAB, Excel, JMP, etc.) .
• Experience in automation and test/integration methodologies.
• Experience developing validation methodologies and infrastructure solutions.
• Test plan and test development experience.
• System and/or Functional area experience .

Job Type:
Intel Contract Employee

Shift:
Shift 1 (United States of America)

Primary Location:
US, Oregon, Hillsboro

Additional Locations:

Business group:
The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust
N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .

Annual Salary Range for jobs which could be performed in the US: $52,000.00-$200,000.00

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
Requisition #: JR0279002

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