Description

Job Details:

Job Description:

Come join Intel's Devices Development Group, responsible for creating leading Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a Pre-Silicon IP Design Verification Engineer, ready to research, design, develop, and test Intel designs as we reimagine how to build SOCs at Intel and in the semiconductor industry. Our bold purpose as a company is to 'create world-changing technology that enriches the lives of every person on earth' and this role is instrumental in furthering our mission to shape the future of technology.

Who You Are
Key Responsibilities:

• Validation of an IP or feature at the IP level.
• Creating plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
• Learning architecture and microarchitecture by debugging failures to the root cause.
• Developing and utilizing various debug and validation tools and/or methodologies to implement validation plans with the goal being to ensure a solid design.
• Participating in the debug of failures on silicon and developing new testing strategies to detect these failures on RTL models.
• Engaging with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution.
• Developing tools and methods to streamline IP development and SOC integration to deliver highest quality in shortest time possible.
• Developing debugging tools and software.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
- Must have either a BS + 2 years' experience or MS + 1 years' experience in Computer Science, Computer Engineering or Electrical Engineering.
- Minimum 2 years experience with reading and interpreting technical specs and Register Transfer Level (RTL) code.
- Minimum 2 years experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog and OVM/UVM.
- Minimum 2 years experience with writing validation plans and software to implement those validation plans.
- Minimum 2 years experience with an object oriented programming language.
- Minimum 2 years experience with Verilog or other HDL.
- Minimum 1 years experience with UNIX or Linux.

Preferred Qualifications:
- Minimum 1 years experience with computer architecture.
- Minimum 2 years experience with validation or testing experience, especially in a silicon design team.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Job Type:
Experienced Hire

Shift:
Shift 1 (United States of America)

Primary Location:
US, Oregon, Hillsboro

Additional Locations:

Business group:
Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust
N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .

Annual Salary Range for jobs which could be performed in the US: $122,440.00-172,860.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Requisition #: JR0281953

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