Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  
• 3 years of experience in high-speed I/O validation, specifically focusing on MIPI, MPHY or USB 3.2 electrical compliance & characterization.
• Experience in Linux, Python & Shell scripting.
• Experience with lab equipment including high-bandwidth oscilloscopes, Bit Error Rate Testers (BERTs), JTAG T32 and Vector Network Analyzers (VNAs).
• Experience in IP bring-up, validation, PCB schematics/Layout, and manufacturing support.
• 
  Experience debugging hardware issues using schematics and layouts.
  
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
  
• Experience with MPHY and USB-IF compliance testing and the official certification process.
• Experience with advanced equalization techniques and their characterization.
• Experience with Python-based automation (electrical measurement equipment, environmental chambers, etc.) and scripting (data analysis, manipulation, visualizations).
• Experience with one or more of the following: PyVISA, Pytest, Pandas, Pywinauto, PyAutoGUI.
• Experience with signal integrity principles and measurement techniques.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a HSIO IP Validation Engineer, you'll help evaluate, test, characterize, and qualify the High-Speed I/O (HSIO) IPs that are part of Google's System-on-Chips (SoCs). In this role, you will be responsible for all aspects of post-silicon validation for critical HSIO interfaces like PCIe, USB, UFS, Mobile Industry Processor Interface (MIPI) (C-PHY/D-PHY), and DisplayPort that power our latest mobile phones, wearables, tablets, and laptops.

You will work closely with ASIC Architecture, Design, and DFT teams in pre-silicon stages to identify, advocate, and implement design for test/manufacturing/debug strategies. During the post-silicon phase, you will be responsible for PHY electrical validation, protocol compliance testing, and system-level interoperability. Your work will involve bare-metal and OS-based validation, PVT characterization, ATE-Bench/SLT-Bench correlation, and supporting complex cross-functional debugging efforts.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Own bench-level design validation and electrical compliance for High-Speed Serial Interfaces (MIPI M-PHY, USB3.2), ensuring certification readiness across PVT operating conditions.
• Characterize signal and power integrity using oscilloscopes, BERTs, and VNAs to perform advanced analysis including eye diagrams, Jitter decomposition, and receiver (Rx) tolerance.
• Collaborate with cross-functional teams to root-cause complex PHY-level electrical issues and protocol link-up failures, driving design corrective actions.
• Design Python-based automation to improve lab efficiency and partner with architecture teams to implement end-to-end manufacturing test solutions.
• Influence next-generation product design via validation feedback and support production teams in developing ATE/SLT screens to reduce Defective Parts per Million (DPPM).

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Requisition #: 72674593424188102

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