Description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in silicon design with a focus on IP (CPU, GPU, or TPU).
• Experience leading technical teams and RTL design projects to tape-out.
• Experience with SoC infrastructure design (e.g., clocking, reset sequences, power intent/UPF).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with ARM architecture and AMBA protocols (AXI, ACE, CHI).
• Experience as a unit lead or design manager for processor projects.
• Understanding of CPU subsystem integration, debug architectures (CoreSight), or secure boot flows.
• Ability to lead distributed teams and execute effectively in a cross-functional environment.

About the jobBe part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Global Design Lead, you will join the CPU Silicon Engineering team to architect and deliver the foundational infrastructure that enables our high-performance processors to function. You will own the "global" logic subsystems within the CPU, encompassing clock generation, reset domains, power management integration, and debug/trace fabrics. In this role, you will lead the technical definition and execution of these critical blocks, ensuring they meet rigorous performance requirements and integrate seamlessly into the top-level System-on-Chip (SoC). You will lead a distributed engineering team through the full design life-cycle, from micro-architecture and RTL implementation to logic synthesis and post-silicon bring-up, while collaborating closely with cross-functional partners to resolve integration issues.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $183,000-$271,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead the micro-architecture, design, and delivery of CPU subsystem infrastructure, including Clocks, Resets, Boot, and Debug/Trace logic.
• Drive the integration of the CPU into the top-level SoC, managing standard interfaces (e.g., AXI, APB, CHI) and cross-functional dependencies.
• Manage the execution of the design life-cycle from concept to tape-out, overseeing logic synthesis, static checks (Lint/CDC), and engineering deliverables.
• Collaborate with verification, physical design, and post-silicon validation teams to ensure functionality and successful bring-up.
• Mentor and manage a technical team, fostering growth and collaboration across multiple global sites.

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Requisition #: 101001826886656710

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